Interaction problems between Intel TSX and Intel performance registers

This document (7023734) is provided subject to the disclaimer at the end of this document.

Environment

SUSE Linux Enterprise Server 15
SUSE Linux Enterprise Server 12
SUSE Linux Enterprise Server 11

Situation

Intel reported that after updating the CPU Microcode on a set of modern Intel processors using Intel® Transactional Synchronization Extensions (TSX) extensions, the Performance Measurement Register 3 is not usable due to technical limitations.

This issue could lead to incorrect performance measurements when register 3 is in use.

It does not affect systems or processes where the registers are not in use.

Affected processors families :

Intel Skylake
Intel Kaby Lake
Intel Coffee Lake
Intel Whiskey Lake

For more details see the Intel whitepaper here : Performance Monitoring Impact of Intel® Transactional Synchronization Extension Memory

Resolution

Solution will be in a new microcode update.

In the interim, Intel's guidance is to avoid usage of the Performance Counter 3 (so only use counters 0 to 2).

SUSE is implementing this guidance and restriction in the perf framework in the Linux Kernel and will release kernel updates containing this restriction.

There is a new kernel boot option added that re-enables all 4 performance counters:

enable_all_counters=on/off

If this option is enabled, usage of TSX will be force-disabled during performance measurement.

The number of available performance counters is exported to userspace over sysfs.

Cause

CPU Microcode update on a specific set of modern Intel processors.

Additional Information

Also there are performance monitor flags that can be used to adjust behaviour :

Add a "force_rtm_abort" attribute per perf event attribute to allow user programs to opt in to use counter 3 and disable TSX while the perf event is active.
Also add a "allow_rtm" attribute to allow programs to make sure TSX is enabled during the measurement (e.g. if they want to measure TSX itself)

Disclaimer

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